The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that includes nonvolatile memory cells and is prepared to be able to perform redundancy defect replacement.
In recent years, the yield of flash memories as nonvolatile semiconductor memory devices tends to decrease with increase in memory capacity and improvement in fine fabrication process technology. To suppress the decrease of the yield, it has become essential to provide semiconductor memory devices that can replace effective memory cell with a spare memory cell (redundancy defect replacement).
The semiconductor memory devices as described above are disclosed. in Japanese Laid-Open Patent Publication No. 5-159597 and the like, for example. FIG. 5 schematically shows an example of such conventional semiconductor memory devices.
Referring to FIG. 5, a regular memory cell array 101 includes memory cells (denoted as MC in FIG. 5) arranged in a matrix to be connected to n regular word lines WL1 to WLn (n is a positive integer) and m bit lines BL1 to BLm (m is a positive integer). A spare memory cell array 102 includes memory cells connected to a word line WLn+1 and the bit lines BL1 to BLm. A redundancy control circuit 104 includes selection circuits Sa1 to San and control cells Ca1 to Can. The selection circuits Sa1 to San switch the connection of signal lines R1 to Rn extending from a row decoder 103 to the corresponding word lines WL1 to WLn+1. Each of the control cells Ca1 to Can includes a fuse element or a nonvolatile memory cell for storing defect information although not shown. The output lines from the control cells Ca1 to Can are connected to the corresponding selection circuits Sa1 to San and the adjacent control cells.
The operation of the semiconductor memory device having the construction described above will be described. The row decoder 103 decodes an input row address and outputs the results to the signal lines R1 to Rn. The selection circuits Sa1 to San perform switching based on the outputs of the control cells Ca1 to Can. Specifically, the i-th selection circuit Sai (1xe2x89xa6i xe2x89xa6n) selects the word line WLi when the output of the control cell Cai is a low level (xe2x80x9cLxe2x80x9d) and selects the word line WLi+1 when it is a high level (xe2x80x9cHxe2x80x9d), for example. The control cell Cai, in which defect information on the regular word line WLi has been stored, outputs xe2x80x9cHxe2x80x9d when the defect information indicates that the word line WLi has a defect or when the output of the control cell Caixe2x88x921 is xe2x80x9cHxe2x80x9d, and otherwise outputs xe2x80x9cLxe2x80x9d. For example, when a defective memory cell MC exists on the i-th word line WLi, defect information indicating this defect is stored in the control cell Cai. In this case, while any selection circuit Sak satisfying 1xe2x89xa6k less than i selects the word line WLk for the signal line Rk, any selection circuit Saj satisfying ixe2x89xa6jxe2x89xa6n selects the word line WLj+1 for the signal line Rj. In other words, the redundancy control circuit 104 shifts the connection of the i-th and subsequent selection circuits to the other word lines so that the defective word line WLi is skipped, to realize redundancy defect replacement.
The above conventional semiconductor memory device has the following problems. The spare memory cell array is used only in the event of replacement of a defect in the regular memory cell array. Therefore, if no such a replacement event has occurred, the spare memory cell array is just left unused while increasing the chip area.
Moreover, when a secondary regular memory region is required for storing a rewrite program in a nonvolatile semiconductor memory device, a memory cell array for the secondary regular memory region needs to be provided in addition to the regular memory cell array and the spare memory cell array. This disadvantageously increases the area of the device.
An object of the present invention is providing a semiconductor memory device capable of providing a secondary regular memory region without increasing the area of the device.
The semiconductor memory device of the present invention includes: a plurality of regular memory cell groups; at least one spare memory cell group arranged in succession to the plurality of regular memory cell groups; a plurality of regular memory cell group selection lines provided respectively for the plurality of regular memory cell groups; at least one spare memory cell group selection line provided for the spare memory cell group; a regular selection circuit connected with a plurality of address selection lines and receiving an address, the regular selection circuit selecting any of the plurality of address selection lines based on the address; a spare selection circuit connected with a spare selection line and receiving a spare selection signal, the spare selection circuit selecting the spare selection line based on the spare selection signal, the spare selection line being connectable with the spare memory cell group selection line; selective connecting means for connecting each of the plurality of address selection lines selectively to a corresponding regular memory cell group selection line among the plurality of regular memory cell group selection lines, at least one of the regular memory cell group selection lines arranged subsequent to the corresponding regular memory cell group selection line, or a spare memory cell group selection line of the spare memory cell group selection lines; a selection control cell group for controlling the selective connecting means so that the regular memory cell group selection lines corresponding to regular memory cell groups excluding a defective memory cell group among the plurality of regular memory cell groups and the spare memory cell group selection line are respectively connected to the plurality of address selection lines; and a register section for holding a spare use flag indicating whether or not the spare selection circuit should select the spare selection line. Whether or not the spare memory cell group is used as a secondary regular memory cell group is determined based on the spare use flag in the register section.
With the above construction, the spare memory cell group can be used for replacing a defective memory cell group or as a secondary regular memory cell group by being selected based on the spare selection signal.
According to the present invention, preferably, the register section outputs a spare selection flag signal based on the held spare use flag, and the spare selection circuit selects the spare selection line based on the spare selection signal when the spare selection flag signal is activated, and keeps the spare selection line in a non-selected state irrespective of the spare selection signal when the spare selection flag signal is inactivated.
With the above construction, control of preventing the spare memory cell group from being selected based on the spare selection signal is possible by use of the flag stored in the register section.
According to the present invention, preferably, the spare memory cell group includes a plurality of spare memory cell groups, and the spare memory cell group selection line includes a plurality of spare memory cell group selection lines respectively corresponding to the plurality of spare memory cell groups, and the device further comprises: spare selective connecting means for selectively connecting the spare selection line to a corresponding spare memory cell group selection line or a spare memory cell group selection line arranged subsequent to the corresponding spare memory cell group selection line; and a spare selection control cell for controlling the spare selective connecting means so that when the corresponding spare memory cell group selection line is used for replacing a defective memory cell group, the spare selection line is connected to the spare memory cell group selection line arranged subsequent to the corresponding spare memory cell group selection line.
With the above construction, it is possible to use part of the plurality of spare memory cell groups for replacing a defective memory cell group, and another part thereof as a secondary regular memory cell based on the spare selection signal.
According to the present invention, preferably, the register section includes spare use flag storing means including a fuse element or a nonvolatile memory cell, and the spare use flag is held in the spare use flag storing means.
With the above construction, the spare use flag can be easily set by programming the fuse element or the nonvolatile memory element.
According to the present invention, the semiconductor memory device further includes: a configuration information memory cell group provided in a common memory cell array with the regular memory cell groups and the spare memory cell group, the configuration information memory cell group including a nonvolatile memory cell for storing the spare use flag; a data read circuit for reading data stored in the memory cell array; and a read control circuit for controlling the data read circuit so that when the spare use flag is read from the configuration information memory cell group by the data read circuit, the read spare use flag is stored in the register section.
With the above construction, the spare use flag information can be written in a memory cell in the common array with the regular memory cells. Therefore, since the common read/write circuits can be used, the circuit scale can be reduced.
According to the present invention, preferably, the semiconductor memory device further includes: a power-on detection circuit for detecting turning on of a power, wherein the read control circuit operates at turning on of the power in response to an output of the power-on detection circuit.
With the above construction, the spare use flag can be set properly only by turning on the power.
According to the present invention, preferably, each of the regular memory cell groups and the spare memory cell group includes nonvolatile memory cells.
With the above construction, the spare memory cell group composed of nonvolatile memory cells can be used as a secondary regular memory region for storing a rewrite program.